TP-LINK TL-MR3020 v1.x

From TechInfoDepot
(Redirected from TP-LINK TL-MR3020)
Jump to navigationJump to search
multiple revisions of this device, use caution
bgn (N150)
Portable 3G Wireless N Router
Homepage
Support
Wikipedia
3rd Party Firmware
dd-wrt
OpenWrt
Tomato any flavor
Incompatible
Gargoyle
Status Unknown
Platform
BrandModelRev
TP-LINK TL-MR3020 v1.x
FCC ID
Board ID
2050500194
Type
mobile router
CPU1
CPU1 Type
MIPS 24K (v7.4)
CPU1 Speed
400 MHz
Flash1 Chip
Spansion S25FL032PIF
Flash1 Size
4 MiB4,194,304 B <br />32,768 Kib <br />4,096 KiB <br />32 Mib <br />0.00391 GiB <br />
RAM1 Size
32 MiB33,554,432 B <br />262,144 Kib <br />32,768 KiB <br />256 Mib <br />0.0313 GiB <br />
RAM1 Chip
Winbond W9425G6JH-6
ETH chip1
Ethernet Port Count
1-100MbE-LAN
Wired Standard
IEEE 802.3i/3u

802dot11 OUI: none specified

Expansion IF types
USB 2.0
USB ports
1
USB Hub Compatible
Untested
Power
5 VDC, 1 A
Connector type
USB Female Mini-B
Flags:
3G capable
Other
Manuf/OEM/ODM
3rd Party Firmware Support
DD-WRT • (List)
, OpenWrt • (List | Dev | DLs)
, libreCMC
Retail
FCC approval date 21 February 2012
(Est.) release date 13 January 2012
UPC 845973051709
(UPC DB, On eBay)
EAN 6935364051709
(UPC DB, On eBay)
ASIN B00634PLTW Flag of the United States.svg
multiple uses
Country of manuf China
Radio 1
Chip1
Wireless interface OUI
none specified
Antenna Connector Type
none specified
MIMO status
1x1:1
Wireless Standard
IEEE 802.11b/g/n
802.11n
up to 150 Mbps
802.11g
up to 54 Mbps
802.11b
up to 11 Mbps
WiFi Operating Frequency
2.4 GHz
 CPU1 brandRadio1 chip1 brandRadio1 chip2 brand
TP-LINK TL-MR3020 v1.xAtherosAtheros
TP-LINK TL-MR3020 v3.xMediaTekMediaTek

For a list of all currently documented Atheros (QCA) chipsets with specifications, see Atheros.

For a list of all currently documented TP-LINK device with specifications, see TP-LINK.

150 Mbps - 1SS 2.4GHz 802.11n (40MHz chan.) = N150 class


Overview

  • TP-LINK TL-MR3020 v3.x (v3/v3.20)
CPU: MediaTek MT7628NN @575MHz WiSoC
Flash: GigaDevice GD25Q64BSIG (8MB)
RAM: Zentel A3R12E40DBF-8E (64MB)
WLAN: 802.11bgn 2T2R (2.4GHz)
LAN: 1x FE, USB: 1x USB 2.0 port
PCB ID: 2050500974

Links of Interest

Flashing

Flashing dd-wrt

Supported by dd-wrt as of = tl-mr3020 build 19342 20120608

Please insert instructions here

Flashing OpenWrt

On the OpenWrt ToH (techdata entry)
On the OpenWrt Wiki
On the OpenWrt Forum
Support started version: 12.09
Current supported version: ?

Please insert instructions here

JTAG-Serial Info

Notes on JTAG

The EJTAG interface AR9331 is different from the ones on most chips:

  • First of all, the Jtag pins are multiplexed with GPIOs, GPIO11 must be pull high to bootstrap the debug interface.
Pressing the SW2 switch while powering on the unit should take care of this as it is connected to GPIO11.
  • The second problem is that U-Boot will disable EJTAG, even if it was enabled by pulling GPIO11 high during power up.
To workaround this, a jumper can be added between the CS pin on the flash and CPU.
  • And last problem is that TP-Link does not provide test points, pads or pins for the Jtag interface.

OpenOCD

This sequence will be needed to initiate PLL and RAM:

PLL / RAM • >>
        #pll initialization
        mww 0xb8050008 0x00018004
        mww 0xb8050004 0x00000352
        mww 0xb8050000 0x40818000
        mww 0xb8050010 0x001003e8
        mww 0xb8050000 0x00818000
        mww 0xb8050008 0x00008000
        sleep 1
        # Setup DDR1 config and flash mapping
        mww 0xb8000000 0x7fbc8cd0
        mww 0xb8000004 0x9dd0e6a8

        mww 0xb8000010 0x8
        mww 0xb8000008 0x133
        mww 0xb8000010 0x1
        mww 0xb800000c 0x2
        mww 0xb8000010 0x2
        mww 0xb8000010 0x8
        mww 0xb8000008 0x33
        mww 0xb8000010 0x1
        mww 0xb8000014 0x4186
        mww 0xb800001c 0x8
        mww 0xb8000020 0x9
        mww 0xb8000018 0xff

        #UART
        mww 0xb8020004 0x4388
        mww 0xb8020008 0xc2000

        #GPIO
        mww 0xb8040028 0x48002

Pictures

Retail Images
User Images