D-Link DIR-456U

From TechInfoDepot
Jump to navigationJump to search
multiple revisions of this device, use caution
bgn (N150)
HSUPA 3G Router Wireless N 150
DIR-456U front.jpg
Wikipedia
WikiDevi.wi-cat.ru
3rd Party Firmware
dd-wrt
OpenWrt
Incompatible
Tomato any flavor
Incompatible
Platform
BrandModelRev
D-Link DIR-456U A1
Model Part Number
IIR456UBNA3GFA1E
FCC ID
Type
wireless router
CPU1
Ralink RT3050
CPU1 Type
MIPS 24KEc
CPU1 Speed
320 MHz 16-bit
Flash1 Chip
Macronix MX29LV320DBTI-70G
Flash1 Size
4 MiB4,194,304 B <br />32,768 Kib <br />4,096 KiB <br />32 Mib <br />0.00391 GiB <br /> (NOR)
RAM1 Size
32 MiB33,554,432 B <br />262,144 Kib <br />32,768 KiB <br />256 Mib <br />0.0313 GiB <br />
RAM1 Chip
ProMOS V54C3256164VDI7
ETH chip1
Ralink RT3050
Switch
Ralink RT3050
Ethernet Port Count
1-WAN
2-100MbE-LAN
Wired Standard
IEEE 802.3/3u,

802dot11 OUI: none specified

Stock bootloader
U-Boot 1.1.3 Ralink UBoot Version: 3.5.1.0
Stock FW OS
Linux 2.6.21
Expansion IF types
6-pin SIM card
SIM Card slot
1
Power
12 VDC, 2 A
Connector type
barrel
Serial Port (UART)
yes
Flags:
3G
Other

Default IP address: 192.168.0.1
the IP 192.168.0.1 is used by 793 additional devices
of which 224 are D-Link devices
Default login user: admin
Default login password: admin
admin:admin credentials used by 1331 additional devices
of which 76 are D-Link devices

Manuf/OEM/ODM
Retail
FCC approval date 23 November 2010
Radio 1
Chip1
Ralink RT3050
Wireless interface OUI
none specified
Antenna Connector Type
none specified
MIMO status
1x1:1
Wireless Standard
IEEE 802.11b/g/n
802.11n
up to 150 Mbps
802.11g
up to 54 Mbps
802.11b
up to 11 Mbps
WiFi Operating Frequency
2.4 GHz
 CPU1 brandRadio1 chip1 brandRadio1 chip2 brand
D-Link DIR-456 rev A1RalinkRalink
D-Link DIR-456URalinkRalink

For a list of all currently documented Ralink chipsets with specifications, see Ralink.

For a list of all currently documented D-Link device with specifications, see D-Link.

150 Mbps - 1SS 2.4GHz 802.11n (40MHz chan.) = N150 class

Overview

"8WHDRV01.2A1G" is silkscreened on the board in the FCC photos.

Links of Interest

JTAG-Serial Info

Serial

Serial Pinouts

Com Speed :57600 Bps Data Bits: 8bit , Parity : None Stop Bit : 1bit Flow control: None


Boot log

Boot log
U-Boot 1.1.3 (Jan 12 2011 - 19:40:43) (ALPHA)                                 
                                                                               
SVN revision: 480                                                             
Target board: WHD-RV01                                                         
                                                                               
Board: Ralink APSoC DRAM:  32 MB                                               
config usb..                                                                   
============================================                                   
Ralink UBoot Version: 3.5.1.0                                                 
--------------------------------------------                                   
ASIC 3052_MP2 (Port5<->None)                                                   
DRAM component: 256 Mbits SDR                                                 
DRAM bus: 16 bit                                                               
Total memory: 32 MBytes                                                       
Flash component: NOR Flash                                                     
Date:Jan 12 2011  Time:19:40:43                                               
============================================                                   
icache: sets:256, ways:4, linesz:32 ,total:32768                               
dcache: sets:128, ways:4, linesz:32 ,total:16384                               
## Powering down port 0 ~ 3.                                                   
                                                                               
Please choose the operation:                                                   
  1: Load system code to SDRAM via TFTP.                                     
  2: Load system code then write to Flash via TFTP.                           
  3: Boot system code via Flash (default).                                   
  4: Entr boot command line interface.                                       
  7: Load Boot Loader code then write to Flash via Serial.                   
  9: Load Boot Loader code then write to Flash via TFTP.                     
 0  ...  3: System Boot system code via Flash. 
 
## Booting image at bf050000 ...
addr:bf050000
We have SEAMA, Image Size = 3727392
Verifying Checksum ...

Uncompressing SEAMA linux.lzma ... OK

## Transferring control to Linux (at address 81f46ec0) ...

## Giving linux memsize in MB, 32

Starting kernel ...

Linux version 2.6.21 (polo@enzo) (gcc version 4.1.2) #1 Fri Dec 17 18:33:21 CST 2010

 The CPU feqenuce set to 320 MHz
CPU revision is: 0001964c
Determined physical RAM map:
 memory: 02000000 @ 00000000 (usable)
Built 1 zonelists.  Total pages: 8128

Pictures

Retail Images
User Images